Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization

ABSTRACT

Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d 1 ≦0.5d 2 , with d 1  being the first layer thickness and d 2  being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d 1 ≦0.3d 2 .

This is a continuation of U.S. Ser. No. 09/642,827 filed Aug. 22, 2000claiming priority to Prov. No. 60/200,002 filed Apr. 27, 2000,incorporated herein by reference.

BACKGROUND OF THE INVENTION

Multi-level metallization is commonly used in the integrated circuitindustry to interconnect various components of a circuit and a system.Metals or metal alloys, such as copper or copper alloys, are used inthese structures due to their low resistivity. FIGS. 1( a)–1(c) show anexample of the fabrication of two parallel metal lines or otherconductive structures in an insulator layer (oxide) 50 grown on asubstrate. In this example, copper (Cu) is used as the conductor.

First, a barrier layer 52 and a seed layer 54 are deposited over thewhole structure as shown in FIG. 1( a). A layer 100 of Cu is thendeposited as shown in FIG. 1( b), by a technique such as electroplating,over the seed layer. The barrier layer, which remains, is not shown inFIG. 1( b). An etching, electrochemical etching, or chemical mechanicalpolishing (CMP) process is then carried out to remove the copper fromthe field regions 58 and leave it in the channels or other types offeatures 56 formed in the insulator layer as shown in FIG. 1( c).

The process of FIGS. 1( a)–1(c) depicts an ideal situation. In practice,it is extremely difficult to obtain the structure of FIG. 1 c. FIG. 2shows the actual cross section of a structure that one may get. Defects,such as dishing 60 and copper remnants 62, can be observed in thechannels or other features 56 and over the field regions 58,respectively. Dishing presents a problem because it produces anon-planar surface and increases the resistance of the line. Copperremnants can cause shorts between conductive lines. These defects can becaused by the CMP process (incomplete removal from the field regions andtoo much removal from the features or channels) as well as by theetching process or the electroetching process.

FIG. 3( a) is a view similar to FIG. 1( b) but is somewhat enlarged andshows the barrier layer 52, which is not shown in FIG. 1( b). FIG. 3( a)also shows only one channel or other type of feature 56 and two adjacentfield regions 58. Feature or channel dimensions can vary widely, but inorder to roughly illustrate the scale of the illustrations provided byFIGS. 3( a)–3(d), it will be assumed that the feature width W in FIG. 3(a) is 100 μm and the feature depth D is 6 μm. FIG. 3( a) alsoillustrates, schematically, the small-grained structure of the Cu layer100 deposited over the barrier layer 52 on the insulator layer 50.

Conventionally, after the Cu layer 100 has been deposited on the barrierlayer overlying the insulator layer 50 as shown in FIG. 3( a), the Culayer is annealed so as to enlarge its grain structure. FIG. 3( b)illustrates, schematically, the relatively large-grained structure ofthe Cu layer 100 after annealing.

The etching, electrochemical etching, or CMP process carried out toremove Cu from the field regions 58 is conventionally performed afterthe annealing operation. FIG. 3( c) shows the structure of the copperlayer 100 after the layer has been partially removed from over the fieldregions 58 by the etching, electroetching, or CMP process. FIG. 3( d)shows the insulator layer and barrier layer structure, with a copperconductive structure remaining in the line, i.e. the channel or othertype of feature 56, after the copper layer has been completely removedfrom the field regions 58 by the selected process. FIG. 3( d) also showsdishing 60 in the copper conductive structure left in the channel orother feature 56 which results from the conventional copper deposition,annealing and copper removal process.

SUMMARY OF THE INVENTION

The present invention proposes an approach to overcome the dishing andcopper (or other conductor) remnant problems mentioned by establishing astructural difference between conductor layers in different regions onthe substrate surface. More specifically, the present invention relatesto a particular process for fabricating conductive structures infeatures of an insulator layer on a substrate, to a layered structureused in such a process, and to conductive structures produced by theprocess. According to the process, a layer of conductive material isapplied over the insulator layer so that the layer of conductivematerial covers field regions adjacent the features and fills in thefeatures. A grain size differential between the conductive materialwhich covers the field regions and the conductive material which fillsin the features is then established by annealing the layer of conductivematerial, and excess conductive material is removed to uncover the fieldregions and leave the conductive structures.

The layer of conductive material is applied so as to define a firstlayer thickness over the field regions and a second layer thickness inand over the features. The first layer thickness and the second layerthicknesses are dimensioned such that d₁≦0.5d₂, with d₁ being the firstlayer thickness and d₂ being the second layer thickness. Preferably, thefirst and second layer thicknesses are dimensioned such that d₁≦0.3d₂.

According to one embodiment of the invention, the layer of conductivematerial over the insulator layer is applied by depositing the layer ofconductive material over the insulator layer, and partially removing thelayer of conductive material from over the field regions to establish adesired thickness differential between the first and second layerthicknesses. According to another embodiment of the invention, the layerof conductive material over the insulator layer is applied by depositinga planarized layer of conductive material over the insulator layer toestablish a desired thickness differential between the first and secondlayer thicknesses.

The layered structure is used in the process and includes the insulatorlayer on the substrate as well as the layer of conductive materialcovering the field regions and filling in the features. A grain sizedifferential between the conductive material which covers the fieldregions and the conductive material which fills in the features isestablished in the conductive material layer by annealing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1( a) is a partial cross-sectional view of a patterned insulatorlayer grown on a substrate surface and having overlying barrier and seedlayers.

FIG. 1( b) is a view similar to FIG. 1( a) showing the insulator layerand Cu layer structure after copper deposition but prior to removal ofCu from over the field regions.

FIG. 1( c) is a view similar to FIG. 1( b) but showing an idealstructure after Cu has been removed from over the field regions.

FIG. 2 is an illustration of defects which may occur when a conventionalcopper deposition, annealing, and copper removal process is carried out.

FIG. 3( a) is a somewhat enlarged view similar to FIG. 1( b) showing thesmall grain structure of the Cu layer as deposited.

FIG. 3( b) is a view similar to FIG. 3( a) but showing the large grainstructure of the deposited Cu layer following an annealing operationwhich conventionally takes place between Cu deposition and removal of Cufrom over the field regions.

FIG. 3( c) is a view similar to FIG. 3( b) but showing the annealed Culayer after it has been partially removed from over the field regions.

FIG. 3( d) is a view similar to FIG. 3( c) showing a dishing defect inthe Cu remaining in an insulator layer channel or other feature after Cuhas been completely removed from the field regions according to aconventional process.

FIG. 4 is a partial cross-sectional view of a layered structure, similarto FIG. 1( b), showing a Cu layer according to the invention, afterannealing, with large grain structure in certain regions and small grainstructure in other regions.

FIG. 5 is a cross-sectional view of a planarized, un-annealed Cu filmaccording to a first embodiment of the invention.

FIG. 6 is a cross-sectional view similar to FIG. 5 but of a partiallypolished, un-annealed Cu film according to a second embodiment of theinvention.

FIGS. 7( a)–7(c) illustrate sequential operations forming part of aninventive process including use of the Cu film shown in FIG. 6.

FIG. 8 is a cross-sectional view, similar to FIG. 1( c), showing animproved conductive structure, barrier layer, and insulator layerstructure, without dishing or conductor remnants, which can be obtainedby the invention.

FIG. 9 is a cross-sectional view similar to FIG. 8 but showing aconductive structure extending beyond adjacent field regions.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 4 represents a novel conductive material layer deposited over apatterned insulator structure. The barrier layer 52 remains disposedbetween the deposited material, which will be presumed to be Cu, and theinsulator layer 50. The novel conductive material layer shown in FIG. 4is distinguished from the conductive material layer shown in FIG. 3( b)in that the novel layer includes built in differences in both chemicalproperties (corrosion rate, etching rate, reactivity, etc.) andstructure (grain size, crystal orientation, porosity/density, etc.).More specifically, the chemical properties and structure of the Cu inand over the channels or various other types of features 56 (hereafterreferred to generally as “features”) are different from the chemicalproperties and structure of the Cu over the field regions 58. Over thefield regions 58, the Cu deposits have small grains and possibly lowdensity. In and over the features, on the other hand, the Cu depositsare dense and display large grain structures.

When the copper layer of FIG. 4 is subjected to an etching,electrochemical etching, or CMP process, it is possible to adjust theprocess parameters such that the material over the field regions 58 isremoved at a rate which is different from the rate at which the materialin and over the features 56 is removed. In other words, the differentialbuilt in the film in terms of its structure is translated into adifferential in the material removal rate. For example, when the film ofFIG. 4 is subjected to an appropriately selected CMP step, the chemicalremoval rate of the small grain regions will be higher than that of thelarge grain regions. Therefore, the material over the field regions 58should be cleaned up first, decreasing and/or eliminating the Cu remnantdefects shown in FIG. 2. Similarly, since the removal rate of materialover the features 56 will be smaller, dishing should also be minimized.The same arguments can also be made for etching and electroetchingprocesses, since small grain materials can generally be etched faster ina given etchant. The important concept here is to build a structuraldifference in material deposited over the field regions and in and overthe features of the substrate so that this structural difference can betranslated into a difference between the chemical/mechanical removalrates of two types of material.

One way of obtaining the structure of FIG. 4 is to initially deposit theCu film in a planar manner so that its thickness is larger over thefeatures and smaller over the field regions. In this way, uponannealing, a differential in grain size can be obtained.

FIG. 5 is a cross-sectional view of a patterned insulator layer 50 onwhich an un-annealed, planarized, copper conductor layer or film 100 hasbeen deposited. One feature 56 is shown. The barrier layer 52 remainsbetween the planarized copper conductor layer 100 and the insulatorlayer 50.

The un-annealed, planarized layer 100 shown in FIG. 5 may be obtained inthe manner disclosed by commonly assigned U.S. patent application Ser.No. 09/201,929, titled METHOD AND APPARATUS FOR ELECTRO CHEMICALMECHANICAL DEPOSITION, filed Dec. 1, 1998, the disclosure of which isincorporated by reference herein. Other commonly assigned U.S. patentapplications also exist that relate to depositing a Cu film on asubstrate and then planarizing the deposited film. Attention is directedto U.S. application Ser. No. 09/283,024, titled METHOD AND APPARATUS FORFORMING AN ELECTRICAL CONTACT WITH A SEMICONDUCTOR SUBSTRATE, filed Mar.30, 1999; Ser. No. 09/285,621, titled METHOD AND APPARATUS FOR PLATINGAND POLISHING A SEMICONDUCTOR SUBSTRATE, filed Apr. 3, 1999; Ser. No.09/373,681, titled METHOD AND APPARATUS FOR DEPOSITING AND CONTROLLINGTHE TEXTURE OF A THIN FILM, filed Aug. 13, 1999; Ser. No. 09/398,258,titled NOVEL CHIP INTERCONNECT AND PACKAGING DEPOSITION METHODS ANDSTRUCTURES, filed Sep. 17, 1999; and Ser. No. 09/483,095, titledSEMICONDUCTOR WORKPIECE PROXIMITY PLATING METHODS AND APPARATUS, filedJan. 14, 2000.

Other commonly assigned U.S. applications which may be of interestinclude Ser. No. 09/466,014, titled A VERTICALLY CONFIGURED CHAMBER USEDFOR MULTIPLE PROCESS; Ser. No. 09/472,523, titled WORK PIECE CARRIERHEAD FOR PLATING AND POLISHING, filed Dec. 27, 1999; Ser. No.09/511,278, titled PAD DESIGNS AND STRUCTURES FOR A VERSATILE MATERIALSPROCESSING APPARATUS, filed Feb. 23, 2000; Ser. No. 09/544,558, titledMODIFIED PLATING SOLUTION FOR PLATING AND PLANARIZATION AND PROCESSUTILIZING SAME, filed Apr. 6, 2000; Ser. No. 09/568,584, titled ANODEASSEMBLY FOR PLATING AND PLANARIZING A CONDUCTIVE LAYER, filed May 11,2000; and Ser. No. 09/621,969, titled PAD DESIGNS AND STRUCTURES WITHIMPROVED FLUID DISTRIBUTION, filed Jul. 21, 2000.

It has been found that the particularly desired grain structuresrepresented in FIG. 4 will result from annealing the Cu film when thethickness of the deposited Cu film over the field regions and thethickness of the film in and over the features have a certainrelationship. Specifically, referring now to FIG. 5, the desired grainstructures will result when the Cu film thickness d₁ over the fieldregions 58 and the Cu film thickness d₂ in and over the features aredimensioned such that d₁≦0.5d₂. Most preferably, the thicknesses aredimensioned such that d₁≦0.3d₂.

Once an un-annealed, planarized, copper conductor layer or film 100 asshown in FIG. 5 has been deposited over the patterned insulator and itsbarrier layer, the film 100 is then annealed to establish the grain sizedifferential.

Annealing is performed to enlarge the Cu grains in the features 56 sothat the grains become as large as possible and voids are eliminated.Annealing parameters (times and temperatures) can be readily determinedby one of ordinary skill in the art of metallurgy. A feature depth D ofabout 6 μm will be presumed by way of example. It will also be assumedthat sufficient un-annealed, planarized, copper conductor film 100 hasbeen deposited so that d₁ in FIG. 5 is roughly 3 μm and d₂ in FIG. 5 isroughly 9 μm. It is to be understood that these dimensions are mentionedas examples only and are not intended to limit the invention in any way.Smaller or larger feature depths D and deposition thicknesses d₁ and d₂can readily be present. Within this framework, numerous annealingprocesses are acceptable. Certain examples of annealing processes willbe mentioned, but the annealing temperatures and annealing timesspecified are not to be considered limiting.

Assuming again that copper is the conductor deposited on the patternedinsulator, annealing can be performed over temperatures ranging, forexample, from about 85° C. to about 250° C. These temperatures are notto be considered limiting. Air may be used as an ambient atmosphere whenannealing is performed in a temperature range of about 85° C.–110° C. Inthis temperature range, annealing can be performed for one hour or more.At higher temperatures, up to about 250° C., annealing will commonly beperformed in an inert or reducing atmosphere to avoid oxidation. Attemperatures of about 200° C.–250° C., annealing can be performed forshorter times of, for example, 1–5 minutes. These times are not to beconsidered limiting. In the range of temperatures between about 110° C.and 200° C., again, annealing will commonly be performed in an inert orreducing atmosphere. As an example, at a temperature of about 150° C.,the copper film 100 could be annealed for approximately one-half hour.Annealing times, however, will depend on the copper conductor filmthickness and can be determined by one of ordinary skill in the art ofmetallurgy without undue experimentation.

After annealing, with the Cu film thicknesses d₁ and d₂ having therelationship mentioned above, the grain structure represented in FIG. 4results. Excess annealed copper is then removed by etching,electroetching, or CMP from over the features and over the field regions58 as will be described.

Various well known chemical compositions are used as etchants andelectroetchants for different types of metal films. These compositionsare well known to those of ordinary skill in the art of metallurgy. Asexamples of these well known compositions, for copper, solutions ofH₂SO₄ (sulphuric acid) and H₂O₂ (hydrogen peroxide) are commonly used asetchants, while, typically, milder acids, such as H₃PO₄ (phosphoricacid), are used as electroetching solutions. Various etching andelectroetching compositions and processes are discussed, for example, inEtching Compositions and Processes, M. J. Collie, Noyes DataCorporation, 1982, p. 3.

The annealed Cu grain size over the field regions 58 (typically lessthan 0.5 μm diameter, average) is substantially smaller than theannealed Cu grain size in and over the features 56 (typically up to andsometimes exceeding 5 μm, average), which is a function of the depth ofthe features. The density of the annealed Cu over the field regions 58,due to voids and other defects, may be in the 97%–100% range, while thecorresponding density of the annealed Cu in and over the features 56 isideally at 100% and, in reality, will be just about 100%. Although thisdensity differential could improve removal properties, it is moreimportant to have present the differential in grain size represented inFIG. 4.

Small grain material has a larger concentration of grain boundaries thanlarge grain material. Grain boundaries are “defective” regions ascompared to the bulk of the grain, and are where etching orelectroetching occurs. Etchants can be formulated to attack grainboundaries, and the rate of chemical attack or chemical etching forsmall grain material will be higher than that for large grain material.The same can be said for the rate of electroetching, since the same sortof material removal mechanism is present. Thus, in the example discussedabove, excess annealed Cu will be removed, by etching or electroetching,from over the field regions 58 before it is removed from over thefeatures 56.

Removal of excess annealed Cu can also be accomplished by CMP. Theremoval of any material by CMP, however, involves (1) a chemicalreaction component, and (2) a mechanical material removal component. Ina CMP material process, if the mechanical component of the process isdoing most of the material removal, then small grain regions of materialcan actually have a lower removal rate than that of large grain regions.By contrast, if the chemical component of the CMP process is moredominant, then large grain regions of material will have the lowerremoval rate. Consequently, in the present application of CMP to removeexcess Cu from over the channels 56 and the field regions 58, the CMPprocess will have to be adjusted so that the chemical component isstrong and the small grain regions are removed faster than the largegrain regions. Such an adjustment may be performed, for example, byusing a relatively reactive chemical composition in the CMP process.

Through the use of etching, electroetching, or a properly selected CMPstep, as described, on the grain structure represented in FIG. 4, thesmall grain Cu over the field regions 58 can be removed more quicklythan the large grain Cu in and over the features 56, and the structureshown in FIG. 8, without dishing or copper remnants, can be obtained.

An alternative way to obtain the structure of FIG. 8 is to start with anun-annealed conductive material film deposited in a conventional,non-planar manner as shown in FIG. 3( a) and then perform, in order,partial polishing, annealing, and additional polishing operations. Thisalternative way will be described with reference to FIGS. 6 and 7(a)–7(c). The conductive material will again be presumed to be Cu.

FIG. 6 is a cross sectional view similar to FIG. 5. However, as opposedto FIG. 5, which shows a planarized, un-annealed film, FIG. 6 shows apartially polished, un-annealed Cu film 100. The structure in FIG. 6corresponds to that shown in FIG. 7( b).

FIG. 7( a) shows a patterned insulator layer 50, a barrier layer 52, anda layer 100 of small grain Cu. As in the known process of FIGS. 3(a)–3(d), the layer 100 of Cu is deposited, by a technique such aselectroplating, over a seed layer originally present on the barrierlayer 52, to obtain the structure shown in FIG. 7( a). As deposited, d₁is approximately equal to d₂. At this point, instead of proceedingdirectly to an annealing step as in the known process represented inFIGS. 3( a)–3(d), a partial polishing operation is performed to reduced₁ and thereby modify the dimensional relationship of d₁ and d₂. It isto be understood that, although a “partial polishing” operation has beenreferred to, any desired material removal process, such as CMP, etching,or electroetching, could be used. Sufficient small grained Cu isremoved, by way of the partial polishing operation, from over the fieldregions 58 so that d₁≦0.5d₂. Most preferably, the thicknesses aredimensioned such that d₁≦0.3d₂.

After a sufficient amount of Cu has been removed from over the fieldregions to bring the thickness d₁ and d₂ into the desired relationship,the small grained Cu is annealed. Annealing produces a differential ingrain size, represented in the layered structure shown in FIG. 7( c),such that after annealing, the Cu grains in and over the features 56 arelarger than the Cu grains over the field regions 58. In this sense, thegrain structure shown in FIG. 7( c) is similar to that shown in FIG. 4.The small grain Cu over the field regions, therefore, can be removedmore quickly than the large grain Cu in and over the features 56, asexplained earlier, by an etching, an electroetching, or an appropriateCMP operation. The structure shown in FIG. 8, without dishing or copperremnants, can be obtained during this final material removal operation.

If certain parameters, such as etchant strength, are adjusted in theparticular material removal process utilized, then other configurationscan be obtained. The cross-sectional view of FIG. 9, for example, showsa Cu or other type of conductive structure which actually extends beyondadjacent field regions 58.

Although the invention has been described in connection with the use ofdepositing Cu, it is similarly applicable to other conductors (metalsand conductive metal alloys) which can be electroplated over asemiconductor substrate. The invention is applicable, for example, todepositing Ni, Au, Pt, Ag, Pd, or Rh on such a substrate.

The foregoing disclosure has been set forth merely to illustrate theinvention and is not intended to be limiting. Since modifications of thedisclosed embodiments incorporating the spirit and substance of theinvention may occur to persons skilled in the art, the invention shouldbe construed to include everything within the scope of the appendedclaims and equivalents thereof.

1. A process of fabricating conductive structures in features of aninsulator layer on a substrate comprising: applying a layer ofconductive material over the insulator layer so that the layer ofconductive material covers field regions adjacent said features andfills in said features; annealing the layer of conductive material toestablish a grain size differential between the conductive materialwhich covers the field regions and the conductive material which fillsin the features by forming small grains in the conductive materialcovering the field regions and large gains in the conductive materialover and filling the features, and removing the conductive material withsmall grains faster than the conductive material with large grains. 2.The process according to claim 1, wherein the layer of conductivematerial is applied so as to define a first layer thickness over thefield regions and a second layer thickness in and over the features. 3.The process according to claim 2, wherein the first layer thickness andthe second layer thickness are dimensioned such that d₁≦0.5d₂, with d₁being the first layer thickness and d₂ being the second layer thickness.4. The process according to claim 3, wherein the first and the secondlayer thicknesses are dimensioned such that d₁≦0.3d₂.
 5. The processaccording to claim 2, wherein applying the layer of conductive materialover the insulator layer includes depositing the layer of conductivematerial over the insulator layer, and partially removing the layer ofconductive material from over the field regions to establish a desiredthickness differential between the first and second layer thicknesses.6. The process according to claim 2, wherein applying the layer ofconductive material over the insulator layer includes depositing aplanarized layer of conductive material over the insulator layer toestablish a desired thickness differential between said first and secondlayer thicknesses.
 7. The process according to claim 5, wherein thefirst layer thickness and the second layer thickness are dimensionedsuch that d₁≦0.5d₂, with d₁ being the first layer thickness and d₂ beingthe second layer thickness.
 8. The process according to claim 7, whereinthe first and the second layer thicknesses are dimensioned such thatd₁≦0.3d₂.
 9. The process according to claim 6, wherein the first layerthickness and the second layer thickness are dimensioned such thatd₁≦0.5d₂, with d₁ being the first layer thickness and d₂ being thesecond layer thickness.
 10. The process according to claim 9, whereinthe first and the second layer thicknesses are dimensioned such thatd₁≦0.3d₂.
 11. The process according to claim 1, wherein the conductivematerial is copper.
 12. The process according to claim 1, wherein theconductive material is a copper alloy.
 13. The process according toclaim 1, wherein removing the excess conductive material is done bychemical mechanical polishing, chemical etching, electrochemicaletching, or any combination of chemical mechanical polishing, chemicaletching and electrochemical etching.
 14. The process according to claim1, wherein establishing the grain size differential also establishes adifferential in chemical removal rates, physical removal rates, or bothchemical and physical removal rates at which the excess conductivematerial can be removed from over the field regions and over thefeatures.
 15. The process according to claim 1, where removing comprisedchemical mechanical polishing having a chemical component dominant overa physical component.